The present invention relates to computing devices and, more specifically, to systems and methods for associating input/output (I/O) requests with memory ranges assigned to particular logical partition (LPAR).
In a computing system, a logical partition (LPAR) is a subset of computer's hardware resources, vitualized as a separate computer. In effect, a physical machine can be partitioned into multiple LPARs, each supporting a separate instance of an operating system.
Each LPAR may access memory from a common memory subsystem, provided that the ranges of addresses directly accessible to each do not overlap. That is, each LPAR may be associated with a particular memory range. Special care is taken to ensure that that one LPAR cannot affect the memory assigned to another LPAR. One LPAR may, however, indirectly affect memory of a second partition, but only by commanding a process of the second partition to directly operate on its memory.
At any given time, an LPAR may be associated with one or more PCIe devices (I/O cards). Typically, multiple I/O cards are coupled to PCIe switches and the LPAR communicates to the individual cards through the PCIe switch.
In some cases, an I/O card or other PCIe device may comply with the Single Root I/O Virtualization (SR-IOV) specification. The SR-IOV specification allows a single PCIe device to represent multiple virtual devices where each virtual device appears to be a separate physical PCIe device. Thus, in the server context, a single I/O card conforming to the SR-IOV specification may be partitioned into multiple virtual devices. Such PCIe devices shall be referred to herein as “SR-IOV devices.” In other cases, the PCIe devices may only represent one device and are referred to herein as “standard PCIe devices.”
In operation, when an LPAR is controlling a PCIe device that device may need to read from or write to the memory associated with the LPAR. It is important that the PCIe device only have access to the memory range associated with the LPAR controlling it. Otherwise, one LPAR may indirectly affect the memory range assigned to another LPAR though memory access operations performed by a PCIe device.
In the case of SR-IOV compliant devices, a function number portion of the requestor ID (RID) identifies the particular virtual device. This function number may be associated with a particular LPAR and the LPAR may instruct the virtual device to use any address in the PCI address space. In the case of a non-SR-IOV compliant devices such a function number is not provided, and firmware may ensure that the addresses in requests made by the device are located within the memory range for the LPAR.
The difference in memory address request formats has required that each PCIe Root Complex be connected to only one of the two types of PCIe devices. In some instances, however, it may be desirable to have both SR-IOV compliant devices and non-SR-IOV devices connected to a single Root Complex through one or more PCIe switches. Current systems may not adequately support such a connection while ensuring PCIe device memory access requests are contained in the memory assigned to the LPAR controlling the PCIe device.